Integrated circuit (IC) technologies are constantly being improved. Such improvements frequently involve scaling down device geometries to achieve lower fabrication costs, higher device integration density, higher speeds, and better performance. Photolithography is frequently used for forming components of an integrated circuit device. Generally, an exposure tool passes light through a photomask or reticle and focuses the light onto a photoresist layer of a wafer, resulting in the photoresist layer having an image of integrated circuit components therein. Printing device patterns with small spacings is limited by a minimum pitch printing resolution of the exposure tool. Double patterning technology (DPT) has thus been implemented to improve pattern resolution as device densities increase. DPT separates a pattern layout into two masks, essentially assigning some features of the pattern layout to one mask and the other features to another mask. Both masks are then used to transfer the pattern layout to a wafer, pushing the photolithography limit.
To achieve pattern layouts that are double patterning compliant, an exemplary DPT method assigns each feature of the pattern layout either a first color or a second color based on various DPT rules. Features assigned the first color are formed on a first mask, and features assigned the second color are formed on a second mask. The DPT rules implemented to decompose the pattern layouts are often complicated, and yet, it has been observed that pattern layouts generated may still not be DPT compliant. Some DPT methods specify that no stitching is allowed, which greatly sacrifices routing flexibility. Accordingly, although existing methods for achieving double patterning compliant pattern layouts have been generally adequate for their intended purposes, as device scaling down continues, they have not been entirely satisfactory in all respects.